An In-DRAM BIST for 16 Gb DDR4 DRAM in the 2nd 10-nm-Class DRAM Process

As the technology node of dynamic random-access memory (DRAM) continues to decrease below 10-nm-class, bit-cell failures due external environments have increased. a result, DRAM vendors perform post package inspections provide fault-free DRAMs end customers. However, require considerable test costs. To overcome this issue, an in-DRAM built-in self-test (BIST) mechanism is implemented in study as alternative solution. Herein, we propose compact and high test-coverage features for BIST that resolve area problem when applied commodity DRAM. The proposed secures same coverage with shorter time than conventional BIST. reduces by 52% DDR functions coverages. Further, can achieved overhead 0.051% based on 16Gb DDR4 second generation 10-nm-class process.